Gigacomís PHY technology based on G-Architecture, provides
high-speed serial data interface (serDes) IP for developing
low-cost, low-power SoC for various networking applications.
The PCIexpress IP family IP which consists of the digital PIPE interface and the mixed-signal transceiver core implements PCIexpess 1.1 and PCIexpress 2.0 protocols. The IP supports various configurations such as endpoint and root complex and is suitable for a variety of applications. The PIPE layer is highly-configurable and implements features such as skip insertion and deletion.
The SATA PHY IP supports SATA 1 and SATA II standards and include the configurable PCS layer. We supply XAUI transceiver for backplane connectivity. It implements protocols including CEI-6, CX4 and KX4 and targets a variety of networking SOC and support a frequency range up to 6.4G.